Subject: Re: Back Annotation Proposal(s)
From: Steve Grout (grouts@flash.net)
Date: Fri Sep 07 2001 - 19:57:12 PDT
Kevin -
Let me first give you, as the group leader on backannotation, my
support for the BA package you posted for our review.
- I do support the approach you detailed in that package as
an update of the current practice. The SPEF/SDF parasitics RC/RCL
update back into the block netlist hierarchy I believe, through
my personal study, can be extended for a couple more technology
generations (down around 0.13u and be successfully used on many
FPGA and ASIC chip designs.)
- There are, though, for even post-0.25u designs and/or higher
performance designs, needs for providing:
+
+
+
+
However, later I would
>
> Steve and Sri,
>
> In-place back-annotation (like SDF) for Verilog-A[MS] requires
> several thing to work. Since current tools generate SPF/SPEF
> (spice netlist), a mechanism to directly read that format is
> desirable (since the files can be very large). A method within
> Verilog-AMS is required for rewiring the design using the
> parasitic and routing data from the SPF, and the semantics of
> A/D insertion should work correctly (i.e. model the circuit
> most accurately) with the "rewired" design.
>
> Reading SPF is covered by the "Filters for foreign languages"
> proposal -
>
> http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0017/index.html
>
> The rewiring syntax is covered by this proposal -
>
> http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/misc/back_ann.pdf
>
> A/D insertion semantics in the rewired design require that disciplines
> can be "process bound" rather than port bound -
>
> http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0002/fllwup-2.html
>
> - which implies that A/D conversion modules are placed on the low side
> of ports -
>
> http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0003/index.html
>
> Using "Filters for foreign languages" proposal does not require us to
> specify any exact translation for spice netlist, and allows vendors to
> recognize their own data formats. Adding the "process bound" attribute
> to a discipline avoids having to change any existing semantics.
>
> Regards,
> Kev.
>
> --
> National Semiconductor
> 2900 Semiconductor Drive, Mail Stop A1-520, Santa Clara, CA 95052-8090
-- --Steve Grout Design Verification, CAD Methodology/R&D, Manager, Individual Contributor - Design Verification, CAD System, Database, Flows, Tools, Integration, and Support for both Digital and Analog/Mixed-Signal Design Teams. 101 Kenneil Court Apex, NC 27502 Phone: 919-303-5066 email: grouts@flash.net http://www.flash.net/~sgrout/Personal/resume2001.txt (or doc,rtf,pdf)
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