Subject: Back Annotation Proposal(s)
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Aug 20 2001 - 13:59:04 PDT
Steve and Sri,
In-place back-annotation (like SDF) for Verilog-A[MS] requires
several thing to work. Since current tools generate SPF/SPEF
(spice netlist), a mechanism to directly read that format is
desirable (since the files can be very large). A method within
Verilog-AMS is required for rewiring the design using the
parasitic and routing data from the SPF, and the semantics of
A/D insertion should work correctly (i.e. model the circuit
most accurately) with the "rewired" design.
Reading SPF is covered by the "Filters for foreign languages"
proposal -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0017/index.html
The rewiring syntax is covered by this proposal -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/misc/back_ann.pdf
A/D insertion semantics in the rewired design require that disciplines
can be "process bound" rather than port bound -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0002/fllwup-2.html
- which implies that A/D conversion modules are placed on the low side
of ports -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0003/index.html
Using "Filters for foreign languages" proposal does not require us to
specify any exact translation for spice netlist, and allows vendors to
recognize their own data formats. Adding the "process bound" attribute
to a discipline avoids having to change any existing semantics.
Regards,
Kev.
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