Subject: Clarification required on Section 8.3.2
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Wed Oct 24 2001 - 22:05:14 PDT
Hi all,
Could somebody clarify this for me with regards to Section 8.3.2...
This section is about
"Accessing X & Z bits of a discrete net in a continuous context" and it
specifies that Verilog-AMS HDL supports comparisons which take account of x &
z bits in continous context since discrete nets can have these values. The
features that are allowed in continuous context are
* case equality (===) operator
* case inequality (!==) operator
* case, casex, casez statements
* numeric constants which can have x & z
However, in the same section there is a paragraph which says...
"All operators, functions and statements are allowed in continuous context,
except for case-equality, case-inequality, case, casex, casez, which shall
report an error if the expressions they operate on contain x or z bits".
Can somebody clarify on this please.
Regards,
Sri
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501 email: schandra@asc.corp.mot.com
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