Subject: Re: Proposal for rewriting Section 8.3.2
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Mon Oct 29 2001 - 10:44:11 PST
> From owner-verilog-ams@eda.org Sun Oct 28 19:26:25 2001
> From: "Srikanth Chandrasekaran" <schandra@asc.corp.mot.com>
> Subject: Proposal for rewriting Section 8.3.2
> To: verilog-ams@eda.org
> cc: ghelwig@asc.corp.mot.com, schandra@asc.corp.mot.com
>
> Hi Committee Members,
> We have worked a proposal for rewriting section 8.3.2 which refers to
>
> Proposal:
> =========
> --------------------------------------------------------------------------------
>
> 8.3.2 "4-state logic processing in continuous context"
>
> The Verilog-AMS HDL provides limited support for accessing and comparing
> 4-state-logic values in the analog context. The following operands
> return 4-state-logic values:
>
> * digital net access (section 8.3.1)
> * binary, octal, hexadecimal numbers (section 2.5).
>
> When the above operands are used in analog context expressions,
> 4-state-logic to integer values conversion are performed (section 8.3.1)
> when the expression is solved. Processing of 'x' and 'z' states is
> vendor specific.
>
> Comparisons of 4-state logic values are limited to case, casez, casex
> statements (section 6.5). All other analog context comparison
> operators (ie. ===, !==) and statements (ie conditional) use real and
> integer types only.
>
>
> Example:
> input net[1:2];
> analog begin
> case(net[1])
> 1'b1: $strobe("net[1] = 1");
> 1'b0: $strobe("net[1] = 0");
> 1'bz: $strobe("net[1] = z");
> 1'bx: $strobe("net[1] = x");
> net[2]:$strobe("net[1] == net[2]");
I don't think you can have a variable as a case target, can you?
> endcase
> end
>
> If "net" is discrete, the "1'bx" and "1'bz" cases are solved without error.
> If the "net" is continuous then the processing of the "1'bx" and "1'bz" cases
> will be vendor specific.
>
> --------------------------------------------------------------------------------
>
> Let us know if you have any issues with this proposal.
"vendor specific" is a bad idea. There is a standing proposal to introduce
NaN, it was intended that arithmetic involving Xs and Zs would return NaN
in a continuous context which would propagate much the same way as X propagates
in a digital context, and that assigning it to a branch would be (runtime) illegal.
It would then be better to consider the values of 4-state logic as floating point
numbers rather than integer in conversion:
1'b0 -> 0.0
1'b1 -> 1.0
1'bZ -> NaN
1'bX -> NaN
NaN can be a case target, and with automatic type casting 1 & 1.0 and 0 & 0.0 are
equivalent.
Note: I would always consider 'net[1]' in your example as being the digital view
of the signal, and there is another standing proposal for conversion of analog
to digital views in procedural code (or vice versa).
Regards,
Kev.
> Thanks & Regards,
> Sri & Graham.
> --
> Srikanth Chandrasekaran
> Global Software Group, EDA SBU
> Motorola Australia.
> Phone: +61-8-8168 3592 Fax: x3501
> email: schandra@asc.corp.mot.com
>
>
This archive was generated by hypermail 2b28 : Mon Oct 29 2001 - 10:45:20 PST