Subject: Proposal for rewriting Section 8.3.2
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Sun Oct 28 2001 - 19:25:15 PST
Hi Committee Members,
We have worked a proposal for rewriting section 8.3.2 which refers to
Proposal:
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8.3.2 "4-state logic processing in continuous context"
The Verilog-AMS HDL provides limited support for accessing and comparing
4-state-logic values in the analog context. The following operands
return 4-state-logic values:
* digital net access (section 8.3.1)
* binary, octal, hexadecimal numbers (section 2.5).
When the above operands are used in analog context expressions,
4-state-logic to integer values conversion are performed (section 8.3.1)
when the expression is solved. Processing of 'x' and 'z' states is
vendor specific.
Comparisons of 4-state logic values are limited to case, casez, casex
statements (section 6.5). All other analog context comparison
operators (ie. ===, !==) and statements (ie conditional) use real and
integer types only.
Example:
input net[1:2];
analog begin
case(net[1])
1'b1: $strobe("net[1] = 1");
1'b0: $strobe("net[1] = 0");
1'bz: $strobe("net[1] = z");
1'bx: $strobe("net[1] = x");
net[2]:$strobe("net[1] == net[2]");
endcase
end
If "net" is discrete, the "1'bx" and "1'bz" cases are solved without error.
If the "net" is continuous then the processing of the "1'bx" and "1'bz" cases
will be vendor specific.
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Let us know if you have any issues with this proposal.
Thanks & Regards,
Sri & Graham.
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501 email: schandra@asc.corp.mot.com
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