Subject: Re: Proposal: Deprecate procedural assign-deassign
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Tue Oct 30 2001 - 11:38:29 PST
> From owner-vlog-pp@eda.org Tue Oct 30 10:37:29 2001
> X-Sender: cliffc@mail.sunburst-design.com
> To: vlog-pp@eda.org, verilog-ams@eda.org
> From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
> Subject: Re: Proposal: Deprecate procedural assign-deassign
>
> At 02:22 PM 10/29/01 -0800, Kevin Cameron x3251 wrote:
> > > Subject: Re: Proposal: Deprecate procedural assign-deassign
> > >
> > > I also agree.
> > > --Steve Grout
> >
> >I seem to remember that the current methodology for driving the
> >resolved value onto signals from auto-inserted A/D conversion modules
> >in Verilog-AMS is something like an assign from procedural code
> >(I'm not sure how anyone is actually implementing it).
> >
> >If it's to be deprecated can we extend force/release to have some
> >kind of optional strength/priority to cover the functionality
> >needed in A/D converters etc?
> >
> >Kev.
>
>
> Can anyone from the Verilog-AMS team shed light on the above statement?
I'll clarify:
The way that Verilog-AMS allows you to mix analog and digital behavior
on a wire is by disconnecting the digital drivers of the wire and
(auto) inserting an D->A conversion module which probes the drivers
to calculate an appropriate analog contribution (voltage or current)
which gets handled by the analog (spice-like) solver. The calculated
analog value for the wire is then driven directly onto the digital
wire by an A->D module (using an assign-like construct).
> In Verilog-1995 and -2001, procedural assign statements are made to
> variable types (such as regs or reals) and variable types do not have
> strengths. Only net types have strengths.
>
> The procedural assign statement also does not resolve with other procedural
> assign statements. In Verilog, last procedural assign statement wins and
> takes control of the variable until another procedural assign statement
> makes an assignment or until a deassign statement, which causes the
> assigned variable to hold its last assigned value until the next normal
> procedural assignment changes the variable. Truely 'tis an ugly construct!
>
> Did Verilog-AMS change this behavior? Am I missing something in this
> discussion?
There didn't seem to be a final solution for the syntax of the assign-like
construct in the A->D modules that everyone was happy with, so I was
thinking we could just do a general purpose mechanism in V++, e.g. use
force/release with some extra priority information indicating what is
doing the forcing (behavioral code,PLI,debug,A->D etc.) and which force
takes priority if there is more than one.
A general purpose mechanism could be used for interfacing to more simulation
environments than just Verilog-A.
Kev.
> Regards - Cliff
>
>
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