Subject: Re: Notes from LRM call on 5th Nov
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Mon Nov 05 2001 - 17:57:26 PST
Fixing some typos in the original mail...
Srikanth Chandrasekaran writes:
#
#Example:
#
# module a2d(dnet, anet);
# input dnet;
# output anet;
# logic dnet;
# wire dnet;
# electrical anet;
#
# analog begin
# case (dnet)
# 1'b1:var = 5;
# 1'bz:var = 2.5;
# 1'b0:var = 0;
# 1'bx:var = avar; // wrong
[SC] 1'bx:var = var; // correct
# endcase
# V(a) <+ var; // wrong
[SC] V(anet) <+ var; // correct
# end
# endmodule
<snip>
Regards,
Sri
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