Subject: Re: Notes from LRM call on 5th Nov
From: Kevin Cameron (dkc@galaxy.nsc.com)
Date: Mon Nov 05 2001 - 18:22:29 PST
Srikanth Chandrasekaran wrote:
> Call to discuss mainly Section 8.3.2:
> -------------------------------------
> Attendees: Kevin Cameroon(National SemiConductors), Jon Sanders(Cadence),
> Graham Helwig, Prasanna Tamhankar, Sri Chandra (Motorola)
> Duration: 1.5 hrs (1:00 - 2:30 PST)
>
> The main issues discussed were
> - accessing digital nets from within analog context
> - accessing digital behaviour from within analog context
>
> * 4-state logic values can be access within analog context. The x and z
> states must be translated to equivalent analog real or integer values
> before being used within the analog context. The case, casex, and casez
> statement and ===, !== operators provide a mechanism to perform this
> conversion.
>
> Example:
>
> module a2d(dnet, anet);
> input dnet;
> output anet;
> logic dnet;
> wire dnet;
> electrical anet;
>
> analog begin
> case (dnet)
> 1'b1:var = 5;
> 1'bz:var = 2.5;
> 1'b0:var = 0;
> 1'bx:var = avar;
> endcase
> V(a) <+ var;
> end
> endmodule
>
I think it was supposed to be:
analog begin
case (dnet)
1'b1:var = 5;
1'bz:var = var; // Hold value (maybe start time-out)
1'b0:var = 0;
1'bx:var = 2.5; // Float it
endcase
V(a) <+ var;
end
> Note: case statement may be replaced with if-else-if statement
> using the case equality operators to perform the 4-state logic
> value comparisons.
>
>
> * Accessing digital net and digital binary constant operands are
> supported within analog context expressions. It is an error these
> operands returns 'x' or 'z' bits values when solved. It will be
> an error if the value of the digital variable being accessed in
> the analog context goes either to 'x' or 'z'.
>
> Example:
>
> reg dnet;
> electrical anet;
> integer var1;
> real var2;
>
> initial begin
> dnet = 1`b1;
> #50 dnet = 1`bz;
> $finish;
> end
>
> analog begin
> var1 = 1'bx; // error
> var2 = 1'bz; // error
> var1 = 1 + dnet; // error after #50
> var2 = 0.35 + dnet; // error after #50
>
> if(dnet == 1'bx); // error
> V(anet) <+ 1`bz; // error
> V(anet) <+ dnet; // error after #50
> end
I would prefer that rather than an error the assignments of x/z translate to NaN,
only the assignment to V(anet) is an error because the matrix is then unsolvable.
For example in simple mux-type logic:
always @ (d1) v1 = F(d1);
always @ (d2) v2 = F(d2)
always @ (posedge clock)
v_out = (select == 0) ? v1 : v2;
V(out) = v_out;
- which is only in error if the value of select gets you a v1 or v2 which is
NaN. I.e. transitional X's & Z's are ignored, if not selected. If select is
X at "posedge clock" v_out would become NaN.
NB: Bad (or experimental) arithmetic can produce NaN anyway, so it should
be handled regardless of X/Z values.
Since Z is an inactive drive it might be worth considering any statement that
is equivalent to:
Branch = number * Z;
as a "null" statement. E.g.:
I(out) = 0;
V(out) = dig_out * 5.0; // Drive 0.0,5.0 or nothing - X is an error.
Of course it's a special case, but I think it may make some sense.
Regards,
Kev.
>
> * Also it was discussed whether the "erroring" of x & z access could be
> overridden using simulator attributes. These conversions could be handled
> by a particular simulator differently but this would be a deviation from the
> standard as defined in the LRM
>
> * The next is planned during the Accelera conference on the 13th of November.
> There is also a face2face meeting planned during the conference at 1:00pm
>
> Let me know if i have misunderstood or misrepresented any of the conversations
> that we had, and also feel free to add any bits that are missing.
>
> Regards,
> Sri
> --
> Srikanth Chandrasekaran
> Global Software Group, EDA SBU
> Motorola Australia.
> Phone: +61-8-8168 3592 Fax: x3501
> email: schandra@asc.corp.mot.com
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