Subject: discipline resolution call notes...
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Thu Dec 06 2001 - 15:09:12 PST
Attendees: Jon (Cadence), Kevin (NSC), Peter (Antrim), David (Avanti), Sri (Mot), Graham (Mot)
Date: Nov. 26th, 3:00pm PST
(Sorry if i had missed anybody who attended the call that day, i think there were two members
from Antrim)
* There was lot of discussion as to how the actual two discipline resolution algorithms (basic
and detailed) translates in terms of where the interface elements are being inserted.
It was discussed that it would be good to have some example models written and explained
through the algorithm where the insertion of the interface elements is done
There is a need to know how these interface elements are inserted if the following techiniques
are used
- basic resolution with split
- basic resolution with merged
- detailed resolution with split
- detailed resolution with merged
Action: All
* There was discussion as to why digital primitives could not be allowed to be instantiated
from an analog block. The reasoning for this being disallowed is the fact that current internal
naming conventions defined in LRM expect port name to be defined for digital primitives also.
- Either come up with a convention which allows digital primitives to be instantiated without
the need to have port names (Sri to check on this)
- Also Jon to check with the cadence elab guys to see why it is necessary and whether the problem
could be got around with having port names
Action: Sri/Jon
* There were issues with analog primitives having the default discipline of electrical and as a language
this would not allow for using these blocks in mechanical & other systems easily.
- electrical was just defined as a starting point
- it was agreed that there is a need to override the discipline of the analog primitive on a
instance to instance basis
- An option of having compile time directives to overcome this issue was discussed
- a default analog discipline (for analog primitives)
- a default digital discipline (for digital primitives)
- default discipline
Action: Jon
* Common user interface to the discipline resolution
* There were discussions on Inherited Connections that cadence has been using.
- Jon to investigate if an Inherited Connection Proposal can be presented by Cadence
* There is also a need to address the back annotation issue, which should be resolved as part of
discipline resolution. It was agreed that the parasitic netlist input should be Verilog-AMS and
not spice, with some conversion defined conversion mechanism from spice to verilog-ams.
* There is a need to send out the X/Z issue after the telephone discussions to close that issue.
Action: Sri to do this from what the understanding was from the discussions. This proposal can
be voted by the members.
* The next call is scheduled for December 10th 3:30pm US PST.
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501 email: schandra@asc.corp.mot.com
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