Subject: Re: port & ground declarations
From: Kevin Cameron (edaorg@v-ms.com)
Date: Thu Mar 14 2002 - 22:21:58 PST
> Hi,
>
> Can ports be declared as ground?
>
> I know LRM doesnt specifically say anything on this issue but just want to get
> an understanding on this.
>
> module blackbox (a,b);
> electrical a;
> ground a;
> endmodule
>
> It is not explicit to the user of this IP that one of the ports inside the
> module is being grounded. Is this desired, or is there a possibility that it
> can be useful? The user of that library can always ground that port by using a
> internal net ground connected to the port while instantiating that module.
I'm seeing a related problem with SystemVerilog - there is no explicit
way to short a signal to ground, power or anything else. The result is
that it folk tend to use port binding mechanisms to do the job.
One of the reasons for not having that mechanism is that signal flow in
digital simulation is mostly unidirectional and folks just use "assign" to
get the desired functionality. Similarly you can create a branch between
any two nodes in Verilog-A and do "V(a,b) <+ 0.0" to get the same effect
as a short-circuit.
The downside is that the fact that the information that two nodes are
actually meant to be the same piece of wire gets buried in behavioral
code and is hard to extract, and simulation is likely to be less
efficient.
I'd like to add an explicit mechanism for shorting wires together e.g.:
module blackbox (a,b);
electrical a;
alias a,ground; // a is equivalent/tied to ground
endmodule
I'd have used "join" or "connect" or "short" instead of "alias" but they've
gone already. BNF ~:
<alias_statement> ::== alias <signal expression>{,<signal expression>}
Comments?
Kev.
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