Subject: Re: port & ground declarations
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Thu Mar 14 2002 - 22:27:31 PST
Kevin,
But why cant we use child instantiation to support this...
The port need not be tied to ground but the language should allow you to
specify something like
electrical internal_net;
ground internal_net;
child chd1(a,internal_net);
which refers to the fact that port "b" in child module is connected to ground
through the internal_net.
Should you be allowed to say within a module that the port is connected to
ground?
ie electrical a; // a is a port
ground a; // port a is actually ground.
The user who uses that library in his design may not be aware of this
if you do that. Just curious.
cheers,
Sri
Kevin Cameron writes:
#
#
#> Hi,
#>
#> Can ports be declared as ground?
#>
#> I know LRM doesnt specifically say anything on this issue but just want to get
#> an understanding on this.
#>
#> module blackbox (a,b);
#> electrical a;
#> ground a;
#> endmodule
#>
#> It is not explicit to the user of this IP that one of the ports inside the
#> module is being grounded. Is this desired, or is there a possibility that it
#> can be useful? The user of that library can always ground that port by using a
#> internal net ground connected to the port while instantiating that module.
#
#I'm seeing a related problem with SystemVerilog - there is no explicit
#way to short a signal to ground, power or anything else. The result is
#that it folk tend to use port binding mechanisms to do the job.
#
#One of the reasons for not having that mechanism is that signal flow in
#digital simulation is mostly unidirectional and folks just use "assign" to
#get the desired functionality. Similarly you can create a branch between
#any two nodes in Verilog-A and do "V(a,b) <+ 0.0" to get the same effect
#as a short-circuit.
#
#The downside is that the fact that the information that two nodes are
#actually meant to be the same piece of wire gets buried in behavioral
#code and is hard to extract, and simulation is likely to be less
#efficient.
#
#I'd like to add an explicit mechanism for shorting wires together e.g.:
#
# module blackbox (a,b);
# electrical a;
# alias a,ground; // a is equivalent/tied to ground
# endmodule
#
#I'd have used "join" or "connect" or "short" instead of "alias" but they've
#gone already. BNF ~:
#
# <alias_statement> ::== alias <signal expression>{,<signal expression>}
#
#
#Comments?
#
#Kev.
#
#
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501
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