Subject: RE: port & ground declarations
From: Martin O'Leary (oleary@cadence.com)
Date: Thu Mar 14 2002 - 22:34:08 PST
Sri,
comments below.
Thanks,
--Martin
> -----Original Message-----
> From: Srikanth Chandrasekaran [mailto:schandra@asc.corp.mot.com]
> Sent: Thursday, March 14, 2002 8:36 PM
> To: Verilog-AMS Committee
> Subject: port & ground declarations
>
>
> Hi,
>
> Can ports be declared as ground?
>
> I know LRM doesnt specifically say anything on this issue but
> just want to get
> an understanding on this.
>
> module blackbox (a,b);
> electrical a;
> ground a;
> endmodule
>
This is prefectly legal according to my reading of the LRM.
> It is not explicit to the user of this IP that one of the
> ports inside the
> module is being grounded. Is this desired, or is there a
> possibility that it
> can be useful?
It doesn't strike me as being especially useful but I don't see
much value in making it illegal.
> The user of that library can always ground
> that port by using a
> internal net ground connected to the port while instantiating
> that module.
>
> cheers,
> Sri
> --
> Srikanth Chandrasekaran
> Global Software Group, EDA SBU
> Motorola Australia.
> Phone: +61-8-8168 3592 Fax: x3501
>
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