Subject: Rep-stop proposal
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Apr 29 2002 - 18:48:40 PDT
Old proposal:
Issue 19: Representation Stops http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0019/index.html
the aim of part B of the "repstop" proposal is to let tools know that some Verilog-A defined primitive
(e.g. a table-driven model or SPICE import) is equivalent to an specific digital primitive simultaneously -
which allows lint-type checking, and also allows users (like NSC) to build libraries that are portable between
simulators (and other tools) with fewer errors.
Kev.
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