Subject: Re: Minutes of the Committee call - 1 July 2002
From: Kevin Cameron (Kevin.Cameron@nsc.com)
Date: Mon Jul 08 2002 - 14:02:08 PDT
Srikanth Chandrasekaran wrote:
> Attendees - Jon (Cadence), Peter, Don (Antrim), Sri, Graham (Motorola)
> Date: 1st July, 4:30pm US PST (2nd July 9:00am Adelaide)
>
> Next Meeting: Scheduled for 8th July, 4:30pm US PST (9th July 9:00am Adelaide)
Sorry I missed the last meeting, I'll try to attend today, but I'll probably be late.
> ....
>
> * There was some concern with regards to the changes that go across the analog boundary. Ex. compatibility with Verilog 2001, System Verilog etc. Sri made a point that it would be difficult to address these issues unless there is the participation of the relavent committee members so that whats being proposed in meaningful and acceptable.
> Question: Should we do the changes for these cases which would make analog more correct without worrying or considering the other side of the fence?
Which changes are those?
> * ....
>
> If anybody else feel that they can contribute to this please do let me know. There pdf and spreadsheet (which has more details) have all the issues listed.
>
> Index Issue Action
> 8 1364 sync-up with $random. Martin
> 11 Issue with genvar. Sync with digital Std Martin
> 14 Ambiguities with current if-else-if syntax/semantics Sri
> 16 Initial Value of wreal set to 0.0 if not defined Jon
> 18 Diagram to reflect example on Section 8.6 Jon
> regarding bi-dir model
> 20 Driver Type function. Kevin
I posted a proposal for that, are there any objections to it, or should I just paste it in?
> 24 LRM cleanup typos Sri
> 25 LRM cleanup - refers to derived disc without Sri
> BNF support for the syntax
> 26 Tri & Wire as alias to be specified Jon
> 27 Syntax inconsistencies between chapter and BNF. Jon
> 6-3, 6-4, 6-5 should reflect BNF
> 48 `include to support both <> and "" Kevin
Ditto.
> 50 Specification of roots for Zi Filter in terms of Z^-1 Peter
> 53 Rules for vector vs scalar connection if the entity Peter
> is reg rather than a wire type
> 60 Values for constants file for charge, boltzmann Sri
> etc should reflect std definitions
> 63 Updating Annex-C with boundstep change Sri
>
>
> The following are the ones that would be good if we can make any progress (irrespective of whether it goes in to LRM 2.1 or not)
>
> 1 Real values ports vs real nets in sync with System Verilog language
> definition.
> 6 Concurrency Problem. LRM does not clearly define MS synchronization
> mechanism for AMS
> 7 LRM does not clearly illustrate the MS simulation cycle. IC analysis
> method is non existent in the current LRM for AMS.
> The general consensus on this one seems that we should adapt what
> VHDL-AMS has done
> 9 Truncating vs Rounding mechanism for converting from analog to digital
> times
- I still have not seen any rationale for truncating, so can I assume it is OK to amend
the LRM to rounding?
> 58 Current LRM makes it illegal to have incompatible continous disciplines
> on the same net. Some of the vendors feel that this will be an useful
> feature to support and allows user complete control.
There has been no proper resolution to the process-bound/port-bound discipline debate. If process-bound
semantics are used for A/D insertion (view conversion), then you can use port-bound for transducer
insertion without confusion. With the current semantics it'll only make a bad situation worse.
Kev.
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