Subject: Another AMS issue
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Jul 08 2002 - 18:21:39 PDT
Another addition in Verilog-AMS is 'wreal' - a wire of type real (that can
be connected through ports). Personnally I'm not very keen on it syntactically
or semantically (not that it's well defined), but it's a useful capability for
mixed-signal modeling.
My objection to wreal is that it adds a keyword and is specific to one type, I
would prefer to use a more general "wire <typedef>" declaration to indicate a
variable is bound to a single physical wire, e.g.
typedef struct {real m,p;} complex;
...
module foo(sig_in,sig_out);
...
wire complex sig_in;
Semantics for handling (AMS) signal resolution and more detail on real valued
nets are described in this document -
http://www.eda.org/verilog-ams/htmlpages/vams_obj.pdf
Anyway, the current questions are:
Will 'wreal' be acceptable in a future SystemVerilog?
If not would 'wire <typedef>' be acceptable? (depracating wreal in Verilog-A)
Feedback appreciated,
Kev.
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