Subject: 'break' statement in Verilog-AMS LRM
From: Srikanth Chandrasekaran (schandra@asc.corp.mot.com)
Date: Mon Aug 12 2002 - 00:30:36 PDT
Hi,
There is no 'break' or 'continue' features that could be used in a loop
construct or case mechanism. Was there any reasoning behind this omission, or
just oversight? Do other feel the need for such a feature. Some of our
designers were mentioning that it would be good to have that feature during
simulation.
cheers,
Sri
-- Srikanth Chandrasekaran Global Software Group, EDA SBU Motorola Australia. Phone: +61-8-8168 3592 Fax: x3501
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