Re: 'break' statement in Verilog-AMS LRM

Subject: Re: 'break' statement in Verilog-AMS LRM
From: Kevin.Cameron@nsc.com
Date: Mon Aug 12 2002 - 01:22:24 PDT

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> From - Mon Aug 12 01:00:32 PDT 2002
>
> Hi,
>
> There is no 'break' or 'continue' features that could be used in a loop
> construct or case mechanism. Was there any reasoning behind this omission, or
> just oversight? Do other feel the need for such a feature. Some of our
> designers were mentioning that it would be good to have that feature during
> simulation.
>
> cheers,
> Sri

You can call 'disable <block_identifier>' from within a block to exit a block
in Verilog (I think) - works like 'break' or 'continue' depending on the context.

Kev.

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