Subject: Rounding of A2D events and the zero-delay inverter behaviour?
From: Graham Helwig (ghelwig@asc.corp.mot.com)
Date: Mon Aug 26 2002 - 00:35:51 PDT
Hello,
From the previous conference call, I'm uncertain how the proposed
change from truncation to rounding of A2D events will reduce the
introduced timing errors.
Section 9.2.2 of the Verilog-AMS LRM version 2.0 describe a zero delay
inverter. This section also describes how a transition propagates from
signal A to B in the first half of a digital time tick. This seems to be
OK. However there is no equivalent example illustrating the affects of
A2D event rounding when the transition occurs within the second half of
the digital time tick. Below I have described my understanding of such
a scenario for the zero-delay inverter based on the proposed changes to
the section 9.2.2.
The diagram (see attachment) describes a transition on analog signal A
starting at ~5.6ns resulting in a A2D event at ~5.7ns. The resulting
digital event on signal A is rounded to the 6ns digital time tick. The
analog process must step to at 6ns before the digital event scheduled at
6ns can be processed (assumption: digital process time <= analog process
time). As a result the analog signal B does not start its transition
until 6ns.
If this behaviour I've described is correct, then a delay of ~0.3ns plus
the analog gate delay is introduced due to rounding of A2D event.
However if the same scenario is performed with truncation of A2D events,
then only the analog gate delay would be introduced. If this behaviour
is not correct, then how should this scenario handled by the
mixed-signal synchronization algorithm? When are the scheduled digital
events from A2D event handled? Can the digital process step forward of
the analog process time?
Regards
Graham
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Graham Helwig email: A11558@email.mot.com
ghelwig@asc.corp.mot.com
Telephone:+61-8-81683532 Fax:+61-8-81683501
Motorola Australia Software Centre,
2 Second Avenue, Mawson Lakes, Adelaide, SA, 5095, Australia
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