Subject: Re: Rounding of A2D events and the zero-delay inverter behaviour?
From: Kevin.Cameron@nsc.com
Date: Mon Aug 26 2002 - 01:49:34 PDT
> From: Graham Helwig <ghelwig@asc.corp.mot.com>
>
> Hello,
>
> >From the previous conference call, I'm uncertain how the proposed
> change from truncation to rounding of A2D events will reduce the
> introduced timing errors.
There's more detail with the issue (see "Specific Case") -
http://www.eda.org/verilog-ams/htmlpages/tc-docs/issues/0001/index.html
Basically if the time step is 1ns in the digital simulator, truncation
has a maximum error of 1ns, and round has a maximum error of 0.5ns.
> Section 9.2.2 of the Verilog-AMS LRM version 2.0 describe a zero delay
> inverter. This section also describes how a transition propagates from
> signal A to B in the first half of a digital time tick. This seems to be
> OK. However there is no equivalent example illustrating the affects of
> A2D event rounding when the transition occurs within the second half of
> the digital time tick. Below I have described my understanding of such
> a scenario for the zero-delay inverter based on the proposed changes to
> the section 9.2.2.
>
> The diagram (see attachment) describes a transition on analog signal A
> starting at ~5.6ns resulting in a A2D event at ~5.7ns. The resulting
> digital event on signal A is rounded to the 6ns digital time tick. The
> analog process must step to at 6ns before the digital event scheduled at
> 6ns can be processed (assumption: digital process time <= analog process
> time). As a result the analog signal B does not start its transition
> until 6ns.
A zero delay assignment does not get rounded, the B event will be at 5.7ns,
it will look the same as having the A2D event at 5.3 (just slid along - see
the newer version of the diagram).
> If this behaviour I've described is correct, then a delay of ~0.3ns plus
> the analog gate delay is introduced due to rounding of A2D event.
> However if the same scenario is performed with truncation of A2D events,
> then only the analog gate delay would be introduced. If this behaviour
> is not correct, then how should this scenario handled by the
> mixed-signal synchronization algorithm? When are the scheduled digital
> events from A2D event handled? Can the digital process step forward of
> the analog process time?
You need to reconsider using a delay in the !A -> B assignment.
BTW, most of this has to do with using existing digital simulators with
a minimum of change, and getting the best accuracy. Ideally a #1 delay
would be 1ns regardless of where it starts, but that would require the
digital kernel doing floating-point scheduling (a major change).
Regards,
Kev.
> Regards
> Graham
>
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