Subject: (Fwd) your question about digital variable access
From: Martin O'Leary (oleary@cadence.com)
Date: Mon Aug 26 2002 - 16:29:05 PDT
Here is an email I sent to Ian a while back in regard
to implicit sensitivity to digital signals.
Thanks,
--Martin
---------------- forward message ---------------------
From: "Martin O'Leary"
Date: Thu, 15 Mar 2001 18:20:38 -0800
To: "Ian Wilson" <imw@antrim.com>, <verilog-ams@eda.org>
Subject: your question about digital variable access
Ian,
In the last meeting you gave a similar example as the following
module mixed1(clk,vout);
wire clk;
electrical vout;
integer np; initial np =0;
always @(posedge clk)
np = np + 1;
analog V(a) <+ np;
endmodule
I understand the question you posed was what values of 'np' should be seen in analog block and when.
In terms of accessing digital variables in the analog block, section 8.3.6.4 of the LRM;
In this case, a digital primary (reg, wire, integer, etc.) whose value is
calculated in the discrete domain appears in an expression which is in the
analog context; thus the analog primary is evaluated in the continuous
domain.
The expression shall be evaluated using the digital value
calculated for the greatest digital time tick which is less than or equal
to the analog time when the expression is evaluated.
This approach does not give very predictable behavior for V(a). Basically the value of V(a) depends on how large a time-step analog takes. In a analog circuit with large time constants, the value of np that analog sees could be very old.
If the model is rewritten such that the analog block is made sensitive to np, it is clearer what the value of V(a) will be as the "@np" ensures that an analog time-point will occur when np changes and hence that V(a) will be updated when np changes.
module mixed2(clk,vout);
wire clk;
electrical vout;
integer np; initial np =0;
always @(posedge clk)
np = np + 1;
analog begin
@np;
V(a) <+ np;
end
endmodule
However because module mixed1 gives such unpredictable behavior, I believe that the LRM should be changed so that adding the event control is not neccessary to get predictable results.
To this end I propose we change 8.3.6.4 of the LRM to the following.
In this case, a digital primary (reg, wire, integer, etc.) whose value is
calculated in the discrete domain appears in an expression which is in the
analog context; thus the digital primary is evaluated in the continuous
domain.
The expression shall be evaluated using the digital value
calculated for the greatest digital time tick which is less than or equal
to the analog time when the expression is evaluated.
If the digital primary's value changes during subsequent digital time ticks
which are less than or equal to the analog time when the expression the
was last evaluated, the analog solution must be recalculated using the
new digital primary value.
--Martin
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