Subject: Re: scheduling semantics for Verilog-AMS (issue 25)
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Sep 16 2002 - 18:33:38 PDT
I presume the paragraphs before this are a copy of the standard Verilog queue processing?
Is the last sentence of 9.3.3.5 complete? - looks like it's missing " are X" or something.
> 9.3.3.6 analog macro-process event scheduling/processing
>
> When a D2A event occurs, then the analog macro-process which is to process this D2A is schedule
> for evaluation on the digital engine event queue. Note that if multiple analog macro-process events
> are scheduled for a particular analog macro-process for a particular time, then a single evaluation of
> the analog macro-process should consume all of these events from the queue.
>
> It also be note that the reason for processing analog macro-processes after other digital events is in
> order to minimize the number of times analog macro-processes are evaluated because such evaluations
> tend to be expensive.
Does this work? If I have an "@(posedge clock)" in my analog block and an "@(posedge clock)" in my
digital, I don't think I want the analog processed after the non-blocking assigns of the digital.
I think you may need to split it into explicit and implicit sensitivity - implicit would be done as you say,
and explicit (@ blocks) at the same time as the digital.
Kev.
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