Subject: Feedback for "updates to LRM proposals" email
From: Graham Helwig (ghelwig@asc.corp.mot.com)
Date: Mon Sep 16 2002 - 22:17:10 PDT
Hello Jon,
Here is some feedback from the OVI committee that was held today.
- Remove "(Cx)" from the text.
- In section 3.5:
- Check formatting of Verilog-AMS code in example.
- Inconsistency wrt. the wreal net ("Wstim" and "wstim") used in
example
- Section 3.6 is redefining section 11.1. Merge section 3.6 body into
section 11.1 and place a reference to section 11.1 in section 3.6.
- In section 3.6.1: If `default_discipline is not defined and a digital
primitive instantiations using implicit nets is present within the
Verilog-AMS description. The text suggests the digital primitive ports
will be resolved to use 'electrical' discipline. This is incorrect for
the case of digital primitive instantiations, since digital primitive
instantiations are syntactically separate from module instantiation
syntax. Digital primitive instantiations will always connect to
primitives with digital ports only. It make sense to be able instantiate
a digital primitive without the need to define a `default_discipline
directive.
- section E3.3: Para 1: line 3: change "... resolved based instance
specific ..." to "... resolved based on instance specific ...".
- section E3.3.2: para 1: line 1: change "If not attribute ..." to "If
no attribute ...".
- section E3.3.2: para 1: line 1: change "... instance of a analog ..."
to "... instance of an analog ...".
- section E3.3.2: para 1: line 6: change "... occur as define is section
..." to "... occur as defined in section ...".
- section E3.3.2: para 1: line 7: change "... are no defined ..." to
"... are no ...".
- section 7.3.3: para 1: line 2: change "... (defined in 3.5)..." to
"...(defined in section 3.5)...".
Also in section E3.3.1, the reference to the 1364-2001 seems out of
place since we are currently synched with 1364-1995 std. Should we be
considering synchronizing with 1364-2001 as soon as possible?
Regards
Graham
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