Subject: Implicit nets in analog and digital behaviour
From: Sri Chandra (schandra@asc.corp.mot.com)
Date: Mon Feb 10 2003 - 22:18:01 PST
Hi all,
Currently implicit nets are not allowed in the behavioural part of the analog syntax and is allowed only in the structural part.
ie.
child chd1(a,b,c); // "c" need not be declared electrical and is a implicit net
analog begin
V(c) <+ 5; // "c" cannot be an implicit net and has to be declared.
end
However, in the digital side of things i am told that Verilog 1364 allows implicit nets as part
of behavioural statements.
Can anybody clarify why there is a discrepancy here? Should digital nets take the "default_discipline" for resolving the net domain?
cheers,
Sri
-- Srikanth Chandrasekaran Global Software Group, EDA Motorola Australia Phone: +61-8-8168 3592 Fax: x3501
This archive was generated by hypermail 2b28 : Mon Feb 10 2003 - 22:18:40 PST