VERILOG-AMS COMMITTEE MEETING

Subject: VERILOG-AMS COMMITTEE MEETING
From: Jonathan Sanders (jons@cadence.com)
Date: Mon Feb 24 2003 - 10:28:12 PST

Colleagues,

This week many engineers and EDA vendors will be discussion various aspects of HDL based design using VHDL and Verilog at DVCon here in San Jose.  The Verilog-AMS committee recently completed our latest revision (2.1) of the Verilog-AMS Accellera standard and have submitted it to the Accellera board for approval.  We are now at the point that we are in need of your participation in both helping to drive the direction of what is next and how to get there.   For this reason we will be having a meeting this Thursday at 3PM to kick off our next round of activities.

The meeting is currently scheduled for this Thursday, February 27th from 3 to 5 PM at Cadence just a few miles from DVCon.  We understand that some of you may not be able to attend in person (although that is desired) so we will be having a call-in number.   The call in number is via RSVP so please send a reply back to this email and I will provide you the call in information. 

Location:  
http://esds.cadence.com/education/esout.mapstock.show_map?p_map_title=CDS-SanJoseCA_Map.gif&p_session_id=20030223375248

555 River Oaks Parkway
San Jose, CA 95134
Building #3  (Little River Oaks Conference Room)
*Note, the above map show you directions to Building 6 which is across the street, this campus is at the corner of Seely and River Oaks.

Topics to discuss are:

-IEEE 1364 Sync up plans
-System Verilog Sync up plans
-Additional Verilog-AMS cleanup and extensions
-Extensions for RF and MEMs
-Extensions for SPICE device model support

If you are unable to attend but desire to join the committee on a regular basis please also let us know and we will make sure you get properly involved.  Also, if you know of others in your company or other companies that should be part of this committee please feel free to share this with them.

If you have any questions please feel free to let me or those on the reflector know.

Looking forward to hearing from each of you,

Jon Sanders

P.S. If you were sent this and are not on the Verilog-AMS reflector and wish to be removed from mailings such as this, please reply back to me and I will remove you from this list.  If you have an alternative from your company that should be on the list please make sure I have that information or that they are on the reflector.

***********************************************************
Jonathan L. Sanders                  
Product Engineering Director
Custom IC Solutions
Cadence Design Systems, Inc.     
555 River Oaks Pkwy
San Jose, CA. 95134
 INTERNET:jons@cadence.com    Tel: (408) 428-5654      Fax : (408) 944-7027
***********************************************************

This archive was generated by hypermail 2b28 : Mon Feb 24 2003 - 10:29:29 PST