Subject: Re: Infinity in Verilog-AMS
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Apr 29 2003 - 11:11:55 PDT
> From Geoffrey.Coram@analog.com Tue Apr 29 10:29:48 2003
>
> Martin -
> The requirement I have is not related to knowing whether the
> parameter was set or not. (Although I like the idea of
> having a way to ask that question.)
>
> The question is in regards to device modeling concepts
> like Early voltages, where the model will do something
> with 1/VA, and it's important to know whether 1/VA
> is really zero or whether it's just "close."
>
> The Cadence Verilog-A Language Reference suggests that I
> Change all illegal references to 'inf to a large number
> such as 1M.
>
> However, 1M (meaning 1e6) is not "large" enough for the
> general case, and probably not even large enough for
> this example.
>
> Perhaps you are meaning that, if a parameter such as the
> Early voltage is not specified, then I could use the
> $param_given construct to make the module behave as
> though VA had a default of infinity.
>
> -Geoffrey
I think you want C's "HUGE" value (from math.h). Like I said, there's
no reason you can't define it in a standard header file (it might be
platform dependent), so there's no real need for a language extension.
I would probably just add it to the constants.vams file e.g.:
`define HUGE 3.40282346638528860e+38
My own favourite is NaN (Not a Number). I'd like it to be defined so
that you can initialize real values with it and assign it when converting
Xs/Zs from digital, and for conditional tests.
Kev.
> Martin O'Leary wrote:
> >
> > Geoffrey,
> > It was removed as inf is not a valid number.
> > Understand the requirement you have - my take is that adding a system task such as $param_given is a better way to know if a parameter was set or not.
> > Thanks,
> > --Martin
>
> --
> Geoffrey J. Coram, Ph.D. Senior CAD Engineer
> Analog Devices, Inc. Geoffrey.Coram@analog.com
> 804 Woburn St., MS-422, Tel (781) 937-1924
> Wilmington, MA 01887 Fax (781) 937-1014
>
>
>
>
>
>
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