Subject: Re: Infinity in Verilog-AMS
From: Geoffrey.Coram (Geoffrey.Coram@analog.com)
Date: Tue Apr 29 2003 - 10:29:34 PDT
Martin -
The requirement I have is not related to knowing whether the
parameter was set or not. (Although I like the idea of
having a way to ask that question.)
The question is in regards to device modeling concepts
like Early voltages, where the model will do something
with 1/VA, and it's important to know whether 1/VA
is really zero or whether it's just "close."
The Cadence Verilog-A Language Reference suggests that I
Change all illegal references to 'inf to a large number
such as 1M.
However, 1M (meaning 1e6) is not "large" enough for the
general case, and probably not even large enough for
this example.
Perhaps you are meaning that, if a parameter such as the
Early voltage is not specified, then I could use the
$param_given construct to make the module behave as
though VA had a default of infinity.
-Geoffrey
Martin O'Leary wrote:
>
> Geoffrey,
> It was removed as inf is not a valid number.
> Understand the requirement you have - my take is that adding a system task such as $param_given is a better way to know if a parameter was set or not.
> Thanks,
> --Martin
-- Geoffrey J. Coram, Ph.D. Senior CAD Engineer Analog Devices, Inc. Geoffrey.Coram@analog.com 804 Woburn St., MS-422, Tel (781) 937-1924 Wilmington, MA 01887 Fax (781) 937-1014
This archive was generated by hypermail 2b28 : Tue Apr 29 2003 - 10:30:10 PDT