Subject: Re: Infinity in Verilog-AMS
From: Graham Helwig (ghelwig@asc.corp.mot.com)
Date: Tue Apr 29 2003 - 23:15:12 PDT
Hello,
There may be other potential uses for 'inf' in analog block
expressions. Consider the following example. What value should 'start'
be set to during IC to avoid @timer() firing in the simulation when
V(in) does not cross zero? Also if 'start' is set to a future simulation
time when v(in) cross zero, what value should 'start' be set to if
that scheduled timer event is to be removed?
if (analysis("ic")) begin
start = ???;
end
@(cross(V(in), 1)) begin
start = $abstime + delta;
end
@(cross(V(in)-offset, 1)) begin
start = ???;
end
@(timer(start)) begin
$strobe("timer has fired");
end
The obvious solution is to assign start some arbitrarily large number
(preferable after the simulation end time). However it may not be large
enough and there is no way of ensuring it is large enough.
The use of `MAX_DOUBLE or `HUGE definition will ensure that the timer()
does not fire unexpectedly. How platform dependent limit values be
defined in either constant.vams or limits.vams. Currently the
Verilog-AMS language provides the simulator has no of determining
platform in order to determine the correct `MAX_DOUBLE or `HUGE
definition.
Using 'inf' key word ensures @timer is not fired unexpected, and the
simulator is responsible to determine the maximum value based on the
platform.
Regards
Graham
Kevin Cameron x3251 wrote:
>
> > From Geoffrey.Coram@analog.com Tue Apr 29 07:30:24 2003
> >
> > Hi, Sri -
> > I was wondering if you (or Kevin) recall why infinity was
> > taken out of OVI-2.0 as an allowed value for parameters.
> > It was allowed in OVI-1.0, but is presently only allowed
> > in ranges, eg, parameter real BV = 1000 from [0:inf).
> >
> > It's something I'd like to see back for device modeling,
> > so I want to know what the reason was and how much
> > resistance we'll face trying to get it back.
> >
> > Thanks.
> > -Geoffrey
> >
>
> Don't know, but I'm sure we can add it back in.
>
> Note: due to issues with adding keywords it's preferable
> to declare things like 'inf' in standard header files
> (like in C). SystemVerilog has a "$root" scope where
> you can declare things like numeric constants (rather
> than using `define).
>
> Kev.
>
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