Subject: Re: Verilog-AMS LRM Device Modeling: May 20
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri May 16 2003 - 09:46:35 PDT
> From owner-verilog-ams@server.eda.org Fri May 16 08:59:23 2003
>
> The second meeting of the Verilog-AMS subcommittee
> for device modeling extensions is scheduled for
>
> Tuesday, May 20, 2003 11 AM US-Eastern Time (8 AM PT)
>
> The dial-in numbers are the same as for the LRM meetings:
> +1-334-309 0262 (Intl)
> +1-866-779 0773 (US)
> Pin number: *3589511* (Including the *)
>
> Agenda is:
> 1) continue building a list of proposed extensions
> 2) update on ADMS's legal status
>
>
> I have heard only from Colin and Laurent about other
> possible extensions to Verilog-AMS. I was hoping to
> hear from a few more.
I had a look at the document under -
http://www.designers-guide.com/private/vams-extensions/compact-modeling/
- and I noticed some overlap with SystemVerilog extensions e.g. I think
1.10 is allowed, 1.7 could be addressed by the use of public & private
attributes of classes, and $root supports 1.14.
The SV 3.1 LRM is available at http://www.eda.org/sv-ec
If anyone is interested we also added an "alias" statement in SV that
allows you to specify wires as being shorted together - previously only
possible by using "jumpered ports".
I would suggest that anyone who has C models for BSIM.X,VBIC,MEXTRAN,
HICUM etc. try re-coding them in Verilog-AMS and list any functionality
missing from Verilog-AMS that makes that difficult. (I'd do it myself
but I'm no modeling expert.)
On extension 1.15 (Frequency Domain descriptions) I would like to start
with extending SV to handle event-driven RF for system level modeling
and then add the RF equivalent of A/D converters for getting between
domains at a later date.
Anyone going to be at DAC?
Regards,
Kev.
---- National Semiconductor, Tel: (408) 721 3251 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
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