Subject: RE: Annex A syntax updates
From: Martin O'Leary (oleary@cadence.com)
Date: Mon Jun 09 2003 - 17:01:59 PDT
Graham,
This looks fine to me.
However I think that the new BNF should not be organized differently from Verilog 2001. It should be clear what the AMS extensions to Verilog are. This, I believe, will make it easier for users and implementers to understand exactly what the AMS extensions are.
Thanks,
--Martin
> -----Original Message-----
> From: Graham Helwig [mailto:ghelwig@asc.corp.mot.com]
> Sent: Tuesday, May 27, 2003 12:58 AM
> To: verilog-ams@eda.org
> Subject: Annex A syntax updates
>
> Hello,
>
> As part of the Verilog-AMS LRM 2.2 work, the analog syntax problems need
> to be fixed. Below is a plan to fix the analog syntax. This will be
> discussed in the next committee meeting.
>
> The major stages are:
>
> 1) Reorganize the syntax within annex A into a more readable and
> navigable format. This only involves moving the syntax around, the
> syntax itself will not be changed.
> 2) Once the reorganization is complete, then review the syntax and
> clean-up any ambiguous, incomplete or wrong syntax.
> 3) Go through the syntax in each section of the LRM and synchronize it
> with the up-to-date syntax in annex A.
>
> For stage 1, the proposed new structure for Annex A is below. Any
> suggestions or improvements are welcome.
>
> A.1 Source text
> A.1.1 Module declaration
> A.1.2 UDP declaration
> A.1.3 Nature definition
> A.1.4 Discipline definition
> A.1.5 Connectrule specification
>
> A.2 Module declarations
> A.2.1 Port declarations
> A.2.2 Parameters declarations
> A.2.3 Genvar declarations
> A.2.4 Branch declarations
> A.2.5 Net declarations
> A.2.6 Variable declarations
> A.2.7 Analog function declarations
>
> A.3 Module constructs
> A.3.1 Module instantiations
> A.3.2 UDP instantiations
> A.3.3 Gate instantiations
> A.3.4 Specify block
> A.3.5 Initial and always blocks
> A.3.6 Analog block
> A.3.7 Continuous assignment
> A.3.8 Default parameter overrides
>
> A.4 Analog behavioural statements
> A.4.1 Contribution and assignment statements
> A.4.2 Timing control statements
> A.4.3 Conditional statements
> A.4.4 Case statements
> A.4.5 Looping statements
> A.4.6 Analog system tasks
>
> A.5 Module expressions
> A.5.1 Constant expression
> A.5.2 Expression
> A.5.3 Genvar expression
> A.5.4 Analog expression
> A.5.4.1 Concatenations
> A.5.4.2 Analog function calls
> A.5.4.3 Analog system functions
> A.5.4.4 Analog probes
> A.5.4.5 Analog operators
> A.5.4.6 Accessing nature attributes
> A.5.4.7 Operators
> A.5.4.8 Primaries
> A.5.4.9 Numbers
> A.5.4.10 Strings
>
> A.6 Module event expressions
> A.6.1 Analog event expressions
> A.6.2 Digital event expressions
>
> A.7 General
> A.7.1 Comments
> A.7.2 Identifiers
> A.7.3 White space
>
> NOTE:
> - A.1.1: contains module, macromodule and connectmodule definitions
> - A.1.2: present for readability. For example:
>
> A.1.2 UDP declaration
>
> udp_declaration ::=
> (See IEEE-1364 1995 std)
>
> - A.3.2: present for readability
> - A.3.3: present for readability
> - A.3.4: present for readability
> - A.3.5: present for readability
> - A.3.6: present for readability
> - A.8.7: present for readability
> - A.5.1: contains any modification to the IEEE 1364-1995
> constant_expression syntax.
> - A.5.2: contains any modification to the IEEE 1364-1995 expression
> syntax.
> - A.5.4: contains the 'expression' and analog_expression syntax used in
> analog block statements only.
> - A.6.2: contains extensions to digital event expressions
> - A.7.2: contains the syntax identifier
>
>
>
> Regards
> Graham
>
>
> --
> -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
> Graham Helwig email: A11558@email.mot.com
> ghelwig@asc.corp.mot.com
> Telephone:+61-8-81683532 Fax:+61-8-81683501
> Motorola Australia Software Centre,
> 2 Second Avenue, Mawson Lakes, Adelaide, SA, 5095, Australia
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