Subject: List of issues planned to be addressed
From: Srikanth Chandrasekaran (srikanth.chandrasekaran@motorola.com)
Date: Mon Jun 09 2003 - 21:57:30 PDT
Hi all,
Here is the list the issues that we plan to address over the period of next 6 months. Each issue has a date identified, on which a proposal is expected to be sent. Depending on when the proposal is sent to the reflector it will be put in the agenda of the appropriate committee meeting.
For details on the description, ownership for the individual issues please refer to the attached PDF file which has the updated information.
Thanks to Martin for sending along his list with tentative dates on it.
The next committee meeting is planned on 15th June 2003, 4:30 PM, US PST. The dial-in numbers are:
+1-334-309 0262 (Intl)
+1-866-779 0773 (US)
Pin number: *3589511* (Including the *)
Regards,
Sri
Item Desc Date
34 $table_model 6/9
5 $random Verilog-A syntax 6/23
29 Bitwise nand/nor 6/23
8 dynamic parameters proposal 7/7
10 Semantics of contribution statements 7/7
28 Indexing of named branches 7/7
33 nature/discipline attributes 7/21
52 @cross initialization issues 7/21
6 Issue with genvar (digital vs analog) 8/4
36 reduction operators 8/4
9 Ambiguities with if-else-if syntax 8/4
53 Support for $fwrite 8/18
39 $fread function 8/18
20 keywords 9/1
31 explitly specifying return UDF values 9/1
30 reg declarations in @initial, @always 9/15
14 Switch branch syntax specification 9/15
49 implicit nets (domainless, wire, nuetral) 9/29
44 usage of implicit nets - clarification 9/29
54 Clarification on args of idtmod 9/29
17 meaning of 'analysis point' 10/13
11 DC Sweep mechanism specification 10/13
19 zi filter issue 10/27
23 Null arguments to laplace/zi 10/27
38 $(f)strobe, $(f)display in analog 11/10
43 timedelay arg semantics for absdelay 11/10
46 Initial value of last_crossing 11/17
47 Section renaming 11/17
50 BNF clarification on module decl 11/17
-- Srikanth Chandrasekaran Global Software Group, EDA Motorola Australia Phone: +61-8-8168 3592 Fax: x3501
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