Subject: RE: $display task in Verilog-AMS
From: Martin O'Leary (oleary@cadence.com)
Date: Tue Aug 12 2003 - 16:01:17 PDT
Sri,
My take is that;
* Changing $display in this way would not be backwardly compatible
* $display is a commonly used system task in digital so should be available in analog and behave in an expected way; $display should only be giving actual converged values not intermediate invalid values.
* The NR-iteration is a solving technique and what happens should not be of much interest to the general user but can be of interest to the power user and the model developer.
* Also along these lines there is an error IMHO in the way $strobe in specified in the analog LRM.
Consider the following code;
for (ii=0; ii< 2; ii = ii + 1) begin
$strobe("strobe gives ",ii);
$display("display gives ", ii);
end
If this code segment is in an analog block I understand from the LRM the result is;
strobe gives 0
display gives 0
strobe gives 1
display gives 1
strobe gives 2
display gives 2
However if this code segment is in a digital block, the result is;
display gives 0
display gives 1
display gives 2
strobe gives 2
In digital, $strobes are not executed until the end of the time tick.
Analog should be changed to be consistent with this.
In analog all $strobes should be executed when a timestep is accepted.
(Note this is one of the issues on the issue list I sent). Note this change is not backwardly compatible but it does make the analog and digital parts of the Verilog-AMS language more consistent and hence makes it easier for users to migrate from using Verilog to using Verilog-AMS.
Thanks,
--Martin
-----Original Message-----
From: Sri Chandra [mailto:schandra@asc.corp.mot.com]
Sent: Tuesday, August 12, 2003 9:07 AM
To: Verilog-AMS LRM Committee
Subject: $display task in Verilog-AMS
Hi,
There was discussion in the device modeling committee in being able to print statements at the end of every iteration as opposed to end of the timestep. The current $strobe syntax in Verilog-AMS prints at the end of every timestep.
The proposal was to have a task called $debug which will print for every iteration. However, currently VerilogAMS also supports a task called $display. The current AMS LRM specifies that $display would be treated same as $strobe. I was wondering instead of introducing a new syntax called $debug whether $display should be used to print every iteration and reuse existing syntax already defined in the language.
$strobe/$fstrobe -- every timestep
$display/$fdisplay -- every iteration
$monitor/$fmonitor -- print if value changes
The language already specifies the file equivalent functions for all these tasks.
Any thoughts?
cheers,
Sri
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