Subject: RE: Error in version 2.1 of the LRM
From: Bakalar, Kenneth (kenneth_bakalar@mentorg.com)
Date: Wed Sep 24 2003 - 12:07:11 PDT
All,
I have always wondered why it was defined that way. It is not, however,
only a typo in the appendix. The same claim (or at least implied claim)
that a single-nature discipline must contain only a potential nature is
made in 1.3.4, 3.4.2.1, 3.8.1 and perhaps elsewhere as well.
Ken (the other Ken)
-----Original Message-----
From: Ken Kundert [ mailto:kundert@cadence.com
<mailto:kundert@cadence.com> ]
Sent: Wednesday, September 24, 2003 2:33 PM
To: Verilog-AMS LRM Reflector
Subject: Error in version 2.1 of the LRM
All,
In the process of putting together documentation on Verilog-AMS I
have found a error in the LRM. On page D-3 of the latest LRM (version
2.1) it gives the discipline for current to be ...
discipline current
potential Current;
enddiscipline
This is incorrect. While it is certainly possible to write the current
discipline this way, doing so violates one of the design goals of the
language, and in the process jeopardizes one of the substantial
advantages that Verilog-AMS has over VHDL-AMS. Allow me to explain. Both
Verilog-AMS and VHDL-AMS support the concept of both conservative and
signal flow models. However, they differ in that in Verilog-AMS you may
freely connect conservative and signal flow models, whereas in VHDL-AMS
you must explicitly use conversion elements to connect them. Since the
in the process of top-down design, one naturally progresses from signal
flow to conservative models, the ability of Verilog-AMS to naturally
interface the two types of components makes it considerably easier and
more efficient to use during a top-down design process.
Today, Verilog-AMS fulfills its promise if the signal-flow models are
written in terms of voltage, but not if they are written in terms of
current. Consider a signal flow voltage amplifier connected to a
resistor ...
module vamp(in,out)
input in; output out;
voltage in, out;
parameter real gain;
analog
V(out) <+ gain*V(in);
endmodule
module resistor(p,n)
electrical p,n;
parameter real r;
analog
V(p,n) <+ r*I(p,n);
endmodule
If these two are interconnected, the potential of the amplifier
(Voltage) is connected to the potential of the resistor (Voltage). These
are compatible and consistent, and so everything works as expected.
Now consider writing a signal flow model for a current amplifier using
the existing current discipline ...
module iamp(in,out)
input in; output out;
current in, out;
parameter real gain;
analog
I(out) <+ gain*I(in);
endmodule
The current discipline defines the Current to be the potential. Thus,
when it connects to the resistor, the amplifiers potential (Current) is
connected to the resistors potential (Voltage), with are both
inconsistent and incompatible.
The original definition for the current discipline was
discipline current
flow Current;
enddiscipline
This version would allow the current amplifier to connect to the
resistor and work as expected, and so it should be restored.
-Ken
This archive was generated by hypermail 2b28 : Wed Sep 24 2003 - 12:07:41 PDT