Subject: RE: VerilogAMS Committee Meeting Minutes - 15 December 2003
From: Chandrasekaran Srikanth-A12788 (Srikanth.Chandrasekaran@motorola.com)
Date: Wed Dec 17 2003 - 20:40:00 PST
Sorry for missing these couple of points. I had them in my notes but it didn't make it to the mail, didn't realize I didn't complete it fully. Thanks to Geoffrey on updating this.
Regards,
Sri
> -----Original Message-----
> From: owner-verilog-ams@eda.org
> [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram
> Sent: Thursday, December 18, 2003 5:41 AM
> To: Chandrasekaran Srikanth-A12788
> Cc: 'Verilog-AMS LRM Committee'
> Subject: Re: VerilogAMS Committee Meeting Minutes - 15 December 2003
>
>
> Sorry about the previous blank message; hit "send" instead of
> "quote" ...
>
>
> I wanted to address two issues here.
>
> > * Strings are currently supported in SystemVerilog and 1364-2001
> > and should probably be resued directly. Also its probably a better
> > idea to sync up with SystemVerilog including all extensions of SV
> > in one shot rather than one feature at a time.
>
> There were two other extensions, variable initialization (at time of
> declaration) and variable declarations in unnamed blocks. I agree
> that it is reasonable to wait for a full sync up with SV for those
> two, since the issues are mainly convenience.
>
> On the issue of strings, however, I think this is really something
> we need in the short term, because people will expect to see models
> for "NMOS" and "PMOS" -- not for type=+1 or type=-1 (especially
> since compact models are traditionally written for NMOS, so model
> writers know type=-1 is a PMOS whereas a designer might expect the
> minus sign to indicate NMOS.
>
>
> > Section 1.4 - Output, operating point parameters
> > * The requirement was to hide certain variables being
> visible outside.
> > The proposal was to declare all the variables at the top level, and
> > making only those variables visible.
> > * In the current language standards, all variables are available to
> > be exposed. However vendors hide internal variables due to
> performance
> > reasons but LRM does allows visibility of all the variables.
>
> A new thought on this would be: what if all parameters and
> module-level variables with (*description="string"*) attributes
> were made visible? This would not affect existing modules, and
> I expect that
> a) compact model writers will attach a description to things
> they want to be visible (gm, cds, etc.), so it would be
> redundant to also specify a second attribute that specifically
> says (*visible="yes"*)
> b) no one will attach a description attribute for something
> they don't want visible -- one would instead use a //comment
>
> -Geoffrey
>
> --
> Geoffrey J. Coram, Ph.D. Senior CAD Engineer
> Analog Devices, Inc. Geoffrey.Coram@analog.com
> 804 Woburn St., MS-422, Tel (781) 937-1924
> Wilmington, MA 01887 Fax (781) 937-1014
>
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