Subject: Re: VAMS for CM: $limit and $previous
From: Kevin Cameron (kcameron@cputech.com)
Date: Fri Jan 16 2004 - 09:33:57 PST
Geoffrey.Coram wrote:
>Ilya -
>Definitely, the model compiler should automatically generate
>the limiting correction. If you build the traditional spice
>RHS, you don't need it anyway.
>
>I don't think we want the model writer to be in charge of
>determining whether limiting occurred. If he makes a
>mistake, or doesn't consider extreme values of the
>parameters, he might say that limiting did not occur
>in a case where the limited V(a,c) is "close enough"
>to the current value. Or, someone might say that
>limiting occurs if the values are not exactly equal,
>which never happens in floating-point arithmetic,
>and the simulator would always see the flag saying
>"limiting occurred, try another iteration."
>
>
I still think you should be able to do everything in Verilog-A, if the C
models
currently built into the simulators are flagging that they aren't happy
a Verilog-A
model should be able to do the same, otherwise folks will continue to use C.
Users can write bad models, but at least it will be debugable if it's in
Verilog-A
unlike the built-in models.
>I think the simulator has to decide when it looks like
>limiting is not important and then perhaps evaluate
>the equations without limiting. Some simulators may
>simply try the equations without limiting (particular
>during transient) and only if an overflow occurs
>would they go back and re-evaluate with limiting.
>
>-Geoffrey
>
It's all trade-off, if you have a smarter solver you can use dumber
models and
vice versa. If you only need a couple of instances in the design to be
"smart" then
you probably want smarter models (for those instances) and a dumber solver.
I think it's a good idea to have some functionality that lets models
indicate they
need more iterations even if the solver ignores the request some of the
time.
Kev.
>Ilya Yusim wrote:
>
>
>>What happens after we limited V(a,c)? For example, if we have some
>>function:
>>
>> I(a,c) <+ f(vd);
>>
>> What we want to happen is:
>>
>> I(a,c) <+ f(vd) + ddx(f(vd), vd) * (V(a,c) - vd);
>>
>>Is this going to be generated implicitly by the model compiler oe should
>>we allow ddx in the expressions?
>>
>>Also, about the 'limited' flag. I realized that the limiting function
>>will not always limit the argument, so it is necessary to tell the
>>simulator whether limiting occurred or not.
>>
>>Ilya
>>
>>
-- Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862
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