Subject: Re: VAMS for CM: $limit and $previous
From: Geoffrey.Coram (Geoffrey.Coram@analog.com)
Date: Fri Jan 16 2004 - 12:25:35 PST
Kevin Cameron wrote:
> I still think you should be able to do everything in Verilog-A, if the C
> models
> currently built into the simulators are flagging that they aren't happy
> a Verilog-A
> model should be able to do the same, otherwise folks will continue to use C.
>
> Users can write bad models, but at least it will be debugable if it's in
> Verilog-A
> unlike the built-in models.
If the VA models converge without having to write a limiting function
or converge without the model-writer having to think about when the
flag should be raised, then I think folks will quickly jump to VA
and let the compiler/simulator take care of the details necessary.
Particularly if it turns out that the right thing to do depends
strongly on the simulator.
Designers don't want to debug a model, whether it's Verilog-A or
built-in.
> It's all trade-off, if you have a smarter solver you can use dumber
> models and
> vice versa. If you only need a couple of instances in the design to be
> "smart" then
> you probably want smarter models (for those instances) and a dumber solver.
I'm sure we all want smarter solvers. :) Ultimately, we want the
solver to "do the right thing" all the time with whatever model
equations it gets from wherever: foundry, Berkeley, etc.
-Geoffrey
This archive was generated by hypermail 2b28 : Fri Jan 16 2004 - 12:31:54 PST