RE: Minutes of: VAMS Compact Modeling conf call May 20

Geoffrey,
That's what I figured.

Verilog doesn't need to know the size at declaration time - it figures it out at elaboration time for each instance of this module based on the size of the passed parameter. Therefore the range should not be mandatory.
(This is what makes writing Verilog simulators such *fun*! ;-) )

I also had a quick look at the SystemVerilog manual.
Link to SystemVerilog manual;
http://www.eda.org/sv/SystemVerilog_3.1a.pdf

and I saw that strings and string parameters are supported there so it seems like this is consistent with what is proposed here.

Thanks,
--Martin

> -----Original Message-----
> From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com]
> Sent: Thursday, May 20, 2004 9:37 AM
> To: Martin O'Leary
> Cc: VerilogA Device Modeling Reflector; verilog-ams@eda.org
> Subject: Re: Minutes of: VAMS Compact Modeling conf call May 20
>
> Martin -
> The string parameter as proposed does have its type defined
> in the declaration statement.
>
> If I have a string parameter like
>
> parameter string type = "nmos" from {"nmos", "pmos"};
>
> then I am saying that the simulator should allocate a 4-character
> string (plus \0 ?) for that parameter; any string that is longer
> than 4 characters must be considered as outside the allowed range
> and thus the simulator does not have to keep track of it.
>
> -Geoffrey
>
>
> Martin O'Leary wrote:
> > > 4. String parameters
> > >
> > > Sri asked if the range (from {"a", "b"}) is mandatory.
> > > This tells the simulator how much space to allocate for the string,
> > > (similar to how digital reg variables have a size), so I believe
> > > it should be mandatory.
>
> > Could someone elaborate more on this point? If the point is that the
> module should indicate the maximum number of chars the string should have
> - this is not correct. In Verilog, parameter sizes and indeed types are
> not finally determined until elaboration time.
Received on Thu May 20 09:57:40 2004