Re: string parameters

I stand corrected: one can have a string parameter in SV.
There are no such examples in the SV LRM that I can find,
but the BNF indicates you can have a parameter of any
data_type.

However, SV does not support ranges for any type of parameter,
as far as I can tell. (Verilog-AMS specifically mentioned
the addition of ranges from 1364-1995, but I see that they
are now allowed in 1364-2005-d2.pdf, so I guess they will
make it over to SV eventually.)

I was trying to make my string parameter consistent with
Verilog's (and V-AMS's) "reg" variable type, which does have
a fixed size.

I guess I don't particularly care if the range is mandatory
or not; if you feel that it's more important to be more
consistent with SV and that the simulator should be able
to dynamically assign sufficient space for an arbirary-length
string, I'll drop the requirement. However, it is important
that the range be an option, and the "range" syntax is
different from that for reals and integers, so the string
parameter declaration can't get folded into that for the
regular parameter declaration syntax.

I'm also a little concerned about the coercion of string
to real listed as an open issue in Annex G.

-Geoffrey

Martin O'Leary wrote:
>
> Geoffrey,
> That's what I figured.
>
> Verilog doesn't need to know the size at declaration time - it figures it out at elaboration time for each instance of this module based on the size of the passed parameter. Therefore the range should not be mandatory.
> (This is what makes writing Verilog simulators such *fun*! ;-) )
>
> I also had a quick look at the SystemVerilog manual.
> Link to SystemVerilog manual;
> http://www.eda.org/sv/SystemVerilog_3.1a.pdf
>
> and I saw that strings and string parameters are supported there so it seems like this is consistent with what is proposed here.
>
> Thanks,
> --Martin
Received on Thu May 20 11:06:07 2004