Re: required parameters

From: Kevin Cameron <kcameron@cputech.com>
Date: Fri May 21 2004 - 17:13:47 PDT

Martin O'Leary wrote:

>The requirement to have default values for parameters is a pretty fundamental thing in Verilog. I think it is unwise for to change this unless we have a very compelling reason. Think that should be up to the Verilog guys to do.
>
>If we need to force a parameters to be required, seems like it would be more consistent with how parameters have been extended in Verilog to create a new parameter keyword called "requiredparam" (like localparam, specparam).
>
>Thanks,
>--Martin
>
>
In what way do you consider it "fundamental", changing it wouldn't break
any existing Verilog.

Adding requiredparam would be as much work, and adds a keyword: all you
would do in the compiler is read it the same as a regular parameter and
flag it as "required".

Anyway, it's really just a parameter forward-declaration so that you can
parse the module, a value may be required if it is used - or not if its
use is guarded by a test for it being set.

The reason for allowing it is to avoid having a bogus default value just
to keep the parser happy, which would then possibly cause an error if
some paramset/instance accidentally misses defining it properly. Digital
Verilog doesn't have as many parameters as device models and their use
is rarely subtle, so that kind of error is less of an issue (but not a
non-issue).

Kev.

>>-----Original Message-----
>>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
>>Behalf Of Geoffrey.Coram
>>Sent: Friday, May 21, 2004 11:25 AM
>>To: Kevin Cameron
>>Cc: VerilogA Device Modeling Reflector; verilog-ams@eda.org
>>Subject: Re: required parameters
>>
>>Kevin Cameron wrote:
>>
>>
>>>It's an elaboration-time check, you wouldn't get as far as running
>>>
>>>
>>simulation, i.e. if the simulator finds a required parameter missing it
>>would not be able to complete elaboration.
>>
>>
>>But there might be a parameter that is only required in some cases,
>>eg an avalanche coefficient only if avalanche is enabled. Then you
>>wouldn't want the elaboration to abort for a missing coeff for a
>>design where avalanche is disabled.
>>
>>-Geoffrey
>>
>
>
>

-- 
Kevin Cameron, CPU Technology, CA 94588, Tel.: (925) 225 4862
Received on Fri May 21 17:13:56 2004

This archive was generated by hypermail 2.1.8 : Fri May 21 2004 - 17:13:59 PDT