RE: required parameters

The requirement to have default values for parameters is a pretty fundamental thing in Verilog. I think it is unwise for to change this unless we have a very compelling reason. Think that should be up to the Verilog guys to do.

If we need to force a parameters to be required, seems like it would be more consistent with how parameters have been extended in Verilog to create a new parameter keyword called "requiredparam" (like localparam, specparam).

Thanks,
--Martin

> -----Original Message-----
> From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
> Behalf Of Geoffrey.Coram
> Sent: Friday, May 21, 2004 11:25 AM
> To: Kevin Cameron
> Cc: VerilogA Device Modeling Reflector; verilog-ams@eda.org
> Subject: Re: required parameters
>
> Kevin Cameron wrote:
> >
> > It's an elaboration-time check, you wouldn't get as far as running
> simulation, i.e. if the simulator finds a required parameter missing it
> would not be able to complete elaboration.
> >
>
>
> But there might be a parameter that is only required in some cases,
> eg an avalanche coefficient only if avalanche is enabled. Then you
> wouldn't want the elaboration to abort for a missing coeff for a
> design where avalanche is disabled.
>
> -Geoffrey
Received on Fri May 21 16:20:34 2004