RE: Accellera's decision on Two Verilogs (fwd)

Hi Everyone and Especially Kevin,
        Kevin, I ask you now to stop your negative activities and focus
only on
What the committees "can do" and NOT "on what it cannot do". If you
continue your negative efforts, you will be asked to leave the
committee, immediately. This is a technical committee and not a
political committee.

        The decision making process within Accellera solely lies within
the Accellera Board. The Accellera organization, represented by
Accellera Board, owns Accellera standards and has the luxury of deciding
what to do with its own standards. As part of our standardization
process, the committee should focus on technical activities. It does has
not have any authority to decide what it can do with Accellera
properties.

        As Sri has explained to you, the plans for Verilog-AMS, which is
approved by Accellera Board is to publish Verilog-AMS that is compatible
with IEEE Verilog 2001 Standard. The next stage is to develop
SystemVerilog-AMS that is compatible to IEEE P1800 (SystemVerilog new
IEEE study group) which is in turn compatible to IEEE Verilog 2001.
There are positive progress within IEEE to ensure that IEEE P1364 for
2005 does not conflict with P1800 (and visa versa).

        Kevin, this is you last warning. I encourage you to work on
technical issues rather than continuing with negative effort.

Best Regards

Vassilios

Accellera TCC.

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Srikanth Chandrasekaran
Sent: Wednesday, June 16, 2004 12:19 AM
To: Kevin Cameron
Cc: Verilog-A Reflector
Subject: Re: Accellera's decision on Two Verilogs (fwd)

Hi Kevin,

Couple of comments (most of what i am going to say is nothing new, and
probably has been often repeated and mentioned by others)

1. VerilogAMS is definitely more compatible with 1364-2001. Infact one
of the threads of the current verilogams work is to make it more
compatible with the latest digitial standard. However, the next IEEE
revision for the 1364 standard is in 2005. I am not sure whether AMS
could make it as part of that standard as it might be very late to
include that as part of the next revision.

The plan is to have a more digital compatible AMS language by later this
year (accellera version 2.3 after the device modeling release of 2.2),
but looks like we will be chasing the digital standard constantly as the
2005 will be released very soon after that.

However, part of migrating to the more current version of 1364 is seen
as a step towards eventually moving to the SV standard.

2. I feel that since SV hasnt become a IEEE standard it will be good to
donate the AMS language as part of SV-AMS standard to IEEE. This depends
on the timeframe that SV has in mind for doing this, and also the effort
and involvement of the members of the SV committee to make this happen
as in my opinion this requires a bigger change in AMS with regards to
the syntax and semantics of the current defintion of AMS.

After having said all this, i personally feel that the AMS committee
should be part of a subcommitte of either SV or 1364 standards to make
it always current with the latest digital standard being released. This
will be useful in a more tight integration of the two languages.

Regards,
Sri

Kevin Cameron wrote:

>
>
> Since SV has not gone to the IEEE-P1364 Working group, but is going to
>
> be a new IEEE committee (if any) I think it re-opens the question as
> to where Verilog-AMS should go next. If AMS is more compatible with
> Verilog-200X than it is with SV I would suggest donating it to the
> IEEE-P1364 Working group may make more sense than trying to merge it
> with SV. That would put it on a more equal footing with VHDL (as far
> as
> standards support goes), and might broaden its appeal.
>
> Comments?
>
> Kev.
Received on Tue Jun 15 21:47:03 2004