>
> Why do you guys talk about macromodules so much?
>
> 1364-2001, 12.1, says,
> "The keyword macromodule can be used interchangeably with the keyword module to define a module."
>
> I.e., macromodules are the same as modules.
>
> Does Verilog-AMS have a special definition of macromodules?
Macromodules (and paramsets) don't introduce extra hierarchy.
Kev.
>
> --
> Shalom Bresticker Shalom.Bresticker @freescale.com
> Design & Reuse Methodology Tel: +972 9 9522268
> Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890
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>
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Received on Tue Jun 22 01:25:44 2004
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