Re: [sv-ec] Re: Quick poll for AMS extension to overload modules

In digital Verilog, that is only in one particular simulator,
and even then, not in all cases.
Most other tools treat macromodules identically to modules.
Thus, macromodule use is non-portable if you need to reference signals inside the macromodule from
outside,
say in a testbench.

Shalom

Kevin Cameron wrote:

> >
> > Why do you guys talk about macromodules so much?
> >
> > 1364-2001, 12.1, says,
> > "The keyword macromodule can be used interchangeably with the keyword module to define a module."
> >
> > I.e., macromodules are the same as modules.
> >
> > Does Verilog-AMS have a special definition of macromodules?
>
> Macromodules (and paramsets) don't introduce extra hierarchy.
>
> Kev.
>
> >
> > --
> > Shalom Bresticker Shalom.Bresticker @freescale.com
> > Design & Reuse Methodology Tel: +972 9 9522268
> > Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890
> > POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478
> >
> > [ ]Freescale Internal Use Only
> > [ ]Freescale Confidential Proprietary
> >

--
Shalom Bresticker                         Shalom.Bresticker @freescale.com
Design & Reuse Methodology                            Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                  Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                      Cell: +972 50 5441478
[ ]Freescale Internal Use Only
[ ]Freescale Confidential Proprietary