> I would think if Verilog-AMS can maintain
>that syntactical equivalence, then it would not be an issue for AMS to add
>to the 1364 a requirement that an AMS implementation shall (required)
>in-line macromodules, while other types of implementations may (optional)
>in-line macromodules, as it is now). I also do not see it as a problem for
>AMS to specify restrictions on macromodules, if needed, in order to in-line
>them.
It would be problematic for an AMS implementation built on top of a 1364
implementation. It would also be problematic for users who want to be
able to use the digital subset of their design in both AMS and digital
Verilog.
Steven Sharp
sharp@cadence.com
Received on Tue Jun 22 15:44:27 2004
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