RE: [sv-ec] Re: Quick poll for AMS extension to overload modules

Hello Shalom,
        As part of Accellera Technical Plans, which were approved last
year by the Accellera Board is to do the following:

1- Develop a version of Verilog-AMS that is compatible with IEEE Verilog
2001. This is what the Accellera Verilog-AMS is doing now. Verilog-AMS
committee is also adding the compact model enhancement. The new LRM will
be released this year. This version is the first step to work in concert
with SystemVerilog standard.

2- Accellera Version 3.0 Of Verilog-AMS Planned for next year will
include modification necessary to create a SystemVerilog-AMS. This will
be done under Accellera with joint committee activities between the
Accellera SystemVerilog members and the full members of Verilog-AMS
committee. We are right now in the early planning stage for this, and we
will publish detail plans once we have agreement within Accellera chairs
and also Accellera Board.

Best Regards

Vassilios

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
Behalf Of Shalom.Bresticker@freescale.com
Sent: Thursday, June 24, 2004 11:04 AM
To: Kevin Cameron
Cc: sv-ec@eda.org; verilog-ams@eda.org
Subject: Re: [sv-ec] Re: Quick poll for AMS extension to overload
modules

Now that is an interesting statement.
Who is going to do that?

> Whatever we do will be merged with SystemVerilog
> (probably next year).

Shalom

-- 
Shalom Bresticker                         Shalom.Bresticker
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