Re: table_model constraints

---"GC" == Geoffrey Coram <Geoffrey.Coram> writes:

GC> Well, we have a Verilog-A interface to our simulator, but
GC> we don't do table models, so where does that leave us?
GC> Shouldn't the LRM be implementable by anyone, at least
GC> to the level of getting the same answer (maybe not as
GC> fast)?

We're in the same boat, and I agree. Leaving this unspecified is an
invitation to spending a lot of time reverse-engineering to get the
'same' answer; a rather frustrating exercise.

--Steve

Steve.Hamm@freescale.com -------------- Mica circuit simulation group
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Received on Wed Aug 11 11:00:18 2004