Re: table_model constraints

Is there a way of specifying a C model interface that would allow folks
to deliver table-driven models as a simulator "plug-in" rather than
having the table models (or other models) as part of the language?

Also, is there an actual stated requirement/rationale for table driven
models somewhere?

Kev.

PS: I did a proposal for SV-CC for runtime loading and binding of
DLLs/SOs which I can dig up if anyone is interested.

Steve Hamm wrote:

>---"GC" == Geoffrey Coram <Geoffrey.Coram> writes:
>
>GC> Well, we have a Verilog-A interface to our simulator, but
>GC> we don't do table models, so where does that leave us?
>GC> Shouldn't the LRM be implementable by anyone, at least
>GC> to the level of getting the same answer (maybe not as
>GC> fast)?
>
>We're in the same boat, and I agree. Leaving this unspecified is an
>invitation to spending a lot of time reverse-engineering to get the
>'same' answer; a rather frustrating exercise.
>
>--Steve
>
>Steve.Hamm@freescale.com -------------- Mica circuit simulation group
> ---- TX32 PL29, 7700 W. Parmer Lane, Austin TX 78729 ----
>
>
>
>

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