derived natures

A question on the designers-guide.com Verilog-AMS Forum:

"Grzegorz Jakacki" wrote:
> Hello,
>
> I have these two declarations in Verilog-AMS:
>
> nature Base ... endnature;
> nature Derived : Base ... endnature;
>
> Neither Base nor Derived define idt_nature.
>
> What is the correct value of Derived.idt_nature ?
>
> There are (at least) two interpretations of LRM, I am not sure
> which one is correct:
>
> (1) Base.idt_nature is not defined, so default is used,
> thus Base.idt_nature==Base. Derived inherits all attributes
> from Base, consequently Derived.idt_nature==Base.
>
> (2) Base.idt_nature is not defined, so Derived does not
> inherit any definition of idt_nature. Consequently
> Derived.idt_nature is not defined. Thus, by default,
> Base.idt_nature==Base and Derived.idt_nature==Derived.
>
> Thanks for any guidance
> Grzegorz

We should add a statement saying which is correct to the next LRM.
Does anyone have a strong opinion?

-Geoffrey
Received on Fri Sep 24 10:45:35 2004