RE: LRM Committee Call - 11/15/04 minute meetings

Once SV has solidified it will be more difficult to get things changed.
We should be trying to get AMS incorporated ASAP. In particular there is
an on-going discussion in the SV-BC about data-types on nets that is
very relevant to AMS, and as far as I can tell no-one on that committee
is particularly interested in mixed-signal issues.

Since there appears to be no other (applicable) active HDL standard
effort,
I can't see an alternative, and the bulk of the semantics and syntax of
SV are defined well enough for the purposes of integrating AMS.

Also, if anyone is interested in doing DSP/RF stuff the extended
data-types in SV will allow easier description of functionality in those
domains.

Kev.

-----Original Message-----
From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com]
Sent: Friday, November 19, 2004 6:22 AM
To: Kevin Cameron
Cc: Verilog-AMS LRM Committee
Subject: Re: LRM Committee Call - 11/15/04 minute meetings

Kevin Cameron wrote: (re merging with IEEE 1364-2001)
>
> SV is still in a state of flux, IMO it would be better to go in at the
deep end and merge with the latest rev of that.
>

Since SV is in a state of flux, I wouldn't know how to try
to merge with it. And the SV people are so busy trying to
get their stuff straightened out, I don't think they have
spare time to help. I vaguely recall that they are
explicitly not considering any extensions to SV3.1a from
Accellera until the first IEEE 1800 standard is balloted.

-Geoffrey
Received on Fri Nov 19 09:37:12 2004