Attendees: Jon Sanders, Jim Barby, Patrick O'Halloran, Martin O'Leary, Shekar Chetput
See below for the minutes for each agenda item.
>-----Original Message-----
>From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On
>Behalf Of Chandrasekaran Srikanth-A12788
>Sent: Monday, November 15, 2004 4:05 PM
>To: Verilog-AMS LRM Committee
>Subject: LRM Committee Call
>
>
>Hi all,
>
>I will not be able to make it for today's schedule LRM committee meeting
>scheduled for 4:30pm US Pacific Time. Given that it's at the last minute I
>would like the call to still go ahead. I will be joining you all for the
>next regular call which would be in two weeks time.
>
>(If for some reason, there arent enough participants or if the call doesn't
>happen - I would like to have the call next Monday - 22nd November, 4:30pm
>Pacific time).
>
>Agenda:
>
>* Merge with IEEE 2001 standard (for which quite an amount of work has
>already been invested, and the draft is in good shape)
Our understanding is that;
This is a first step for SV.
The syntax has already been reviewed last summer and agreed.
Next Steps:
* Roll changes into sections along with semantic notes
* Incorporate things of value to analog from V2001 into the analog block e.g. file reading, variable initialization.
AI: Jon to prepare the list of the potential items. Committee to go through at the next meeting and make a recommendation for each and add additional items if required.
* Resolve any potential conflicts with V2001 and existing Verilog-AMS e.g. the genvars.
>* Resolve the keyword conflict in discipline logic with SV
AI: Martin to send proposal for this.
>* Updates to $table_model proposal.
Martin said that Cadence customers wanted variable spacing.
Patrick said he understood that Agilent also need variable spacing.
The following web site;
www.mathalacarte.com/c/math77_head.html
gives a list of various algorithms that could apply to this problem.
Committee proposed that $table_model is a flexible, general purpose way to model measured data. It should not focus on device table models for fastSPICE simulators for which performance not flexibility is key.
AI: Geoff to confirm that this is in agreement with device modeling committee.
Notes from discussion.
* We need to define situations which are error conditions because of insufficient data.
* AI: All - is scattered or is variable grid on isolines acceptable?
* AI: Patrick to send a ref for definition of "variable grid on isolines"
* Issue: Additional information is very desirable when supply a table - e.g. where are the isolines? - what are the reltol, abstol of the measured points?
How should that information be passed?
AI: Martin to check if you can pass arguments to system tasks by name in SV as this could be a convenient mechanism.
* Issue: Do we need to provide a precise algorithm in the LRM? Or is a more general description okay.
* Issue: Perhaps true scattered data would only be supported with linear interpolation.
>* Extend mixed signal analysis scheduling semantics and algorithm for non
>transient analysis (DCSweep, AC, Noise etc)
Waiting for a proposal from Sri on this.
People on the call were in agreement that small signal analyses should not effect digital.
>* How do we go about SystemVerilog and integration of AMS with SV.
* AI: Sri to find SystemVerilog expert(s) to describe the differences and help with the integration.
* Process would then be to go through the same steps as syncing with V2001; syntax first, then look for conflicts, then value-add.
* Committee expect that this will be a lot of work. Not clear how long it will take. Also see that SV is a moving target which also makes this challenging.
* Issue: Committee should also examine important requests from the A/MS user base - e.g. RF support.
* Issue: Committee should also get closure on clean-up items and typos.
>
>Call Details:
>
>Date: 15 Nov 2004
>Time: 4:30pm Pacific Time
>Dialin Number & Passcode:
>----------------------------------------
>USA Toll Free Number: 877-346-8823
>USA Toll Number: +1-203-320-0407 (for international call-in) PARTICIPANT
>PASSCODE: 602538
>
>Cheers,
>sri
>--
>Srikanth Chandrasekaran
>Freescale Semiconductors, Australia
>Ph: +61-8-8168 3592 Fax: 3501
Received on Tue Nov 16 21:49:19 2004
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