proposal to resolve AMS - SystemVerilog logic conflict (v2.0)

Here is my proposal to resolve AMS - SystemVerilog contradictory uses of logic declarations.

Note: The replacement name for logic in AMS is different than what I proposed earlier this year because from playing around with example usages, I feel it is important that the replacement name is more distinct.

Thanks,
--Martin

Problem:
AMS and SystemVerilog both use 'logic' in a contradictory way.

This prevents people for mixed AMS and SystemVerilog in the same parse stream.

It also is going be a serious roadblock for creating SystemVerilog-AMS.

In AMS, logic is discipline defined in the standard discipline header file; disciplines.vams;

        discipline logic
        domain discrete;
        enddiscipline

To make declare a net called n as having logic discipline in AMS one does;

        logic n;

SystemVerilog adds another 4-value data type, called logic (see Sections 3.3.2 and 5.6 of the SystemVerilog 3.1a LRM).

To create a logic variable called n, one does;

        logic n;

Note logic is almost exactly identical to 'reg' except logic can be declared inside other things (like a struct).

Solution:

In AMS, the logic discipline defined in disciplines.vams should be removed and replaced by a definition for a discrete discipline that is;
        1. compatible with System Verilog
        2. will stand out in some way because in SystemVerilog, users can define new types.

To this end I propose;
ddiscrete (short for discipline discrete)

Because;
1. wire types in Verilog start with 'w' - this makes them easy to recognise. Why not apply a similar conventions to at least digital disciplines?
2. The ddiscrete makes more sense than say dlogic because the discipline is for a discrete types not for logic types (which maybe in the future, users may be able define a continuous logic type using SV-AMS).

A disciplines2.2.vams file == to the disciplines.vams file in LRM2.2 should be supported for backward compatability.

All examples/text in the LRM that use logic should be changed to ddiscrete.

        discipline ddiscrete
        domain discrete;
        enddiscipline
Received on Mon Nov 29 12:00:51 2004